Subject: hurdy problems...
From: "Dr.Godfried-Willem RAES" <[email-masked]>
To: [email-masked]
Date: Sun, 27 Jun 2004 18:06:53 +0200

>Beste Johannes,

ik heb me al een paar dagen suf gewerkt op Hurdy. Er zit toch nog een en 
ander niet snor met de PIC kode.
Een rapportje staat in de bijlage, met de Hurdy Specs.

Groetjes,

Godfried.

___________________________________________________
Dr.Godfried-Willem RAES
LOGOS FOUNDATION
Center for Experimental Music Production
Postal adress: Kongostraat 35
Logos Tetrahedron concert hall: Bomastraat 
26-28
9000 
GENT   BELGIUM 

tel.:[32]-9-2238089                    fax.:[32]-9-2250434
email:  [email-masked]
VISIT LOGOS' LIVELY WEBSITE:   http://logosfoundation.org

PIC Mapping for <hurdy>:
************************
Version 1.1 - 19.06.2004
Version 1.2 - 28.06.2004...

Problemen:
1. PIC1: werkt in grote lijnen, maar regelmatig geeft ie het op en reageert niet meer op midi inputs. (Probleem met cirkulaire buffer in PIC kode???)
2. PIC2: lampjes kode werkt o.k. 
	Motor besturing: verliest om de haverklap de PWM output. Alleen wanneer ik heel vaak alsmaar dezelfde volume kontroller doorstuur, werkt het. Ook de switches verliezen hun logische status, en gaan zelfs in Hi-Z toestand.
	De PWM loopt geinverteerd!
	Ook de switches lijken geinverteerd te werken (als ze werken).
	Motor mag niet reageren op note ON/Note offs. Wel op all notes off.
3. PIC3: dit loopt helemaal niet. Er komt geen PWM uit. Soms -waarom?- wel enkele ON/OFF's, daarna steevast niks meer.
	Ook hier moet de PWM geinverteerd worden. Key pressure moet ook geimplementeerd zijn!

Godfried.

Hurdy = midi channel 9 (offset 0)

Overview:
<Hurdy> is controlled by 3 PIC controllers:
PIC1 is used for the tangent solenoids:
     - 1 data byte (RB0 to RB7, bits flipped), 6 note latch adresses: RA0 to RA5

	let n = midi number of lowest note (openstring low string)
       This pic should behave as follows:
       on reception of NOTE ON command:
' first string
n	set bit 0 in latch 0, reset all other bits in latch 0,1,2 (no solenoid connected)
n+1	set bit 1 in latch 0, reset all other bits in latch 0,1,2 (solenoid 1 ON)
n+2 	set bit 2 in latch 0, reset all other bits in latch 0,1,2 (solenoid 2 ON)
n+3	set bit 3 in latch 0, reset all other bits in latch 0,1,2 (solenoid 3 ON)
n+4	set bit 4 in latch 0, reset all other bits in latch 0,1,2 (solenoid 4 ON)
n+5	set bit 5 in latch 0, reset all other bits in latch 0,1,2 (solenoid 5 ON)
n+6	set bit 6 in latch 0, reset all other bits in latch 0,1,2 (solenoid 6 ON)
n+7	set bit 7 in latch 0, reset all other bits in latch 0,1,2 (solenoid 7 ON)
n+8	set bit 0 in latch 1, reset all other bits in latch 0,1,2 (solenoid 8 ON)
n+9	set bit 1 in latch 1, reset all other bits in latch 0,1,2 (solenoid 9 ON)
n+10	set bit 2 in latch 1, reset all other bits in latch 0,1,2 (solenoid 10 ON)
n+11	set bit 3 in latch 1, reset all other bits in latch 0,1,2 (solenoid 11 ON)
n+12	set bit 4 in latch 1, reset all other bits in latch 0,1,2 (solenoid 12 ON)
n+13	set bit 5 latch 1, bit 1,latch 0, reset other bits in latch 0,1,2 (solenoid 1 & 13 ON)
n+14	set bit 6 latch 1, bit 2,latch 0, reset other bits in latch 0,1,2 (solenoid 2 & 14 ON)	
n+15	set bit 7 latch 1, bit 3,latch 0, reset other bits in latch 0,1,2 (solenoid 3 & 15 ON)
n+16	set bit 0 latch 2, bit 4,latch 0, reset other bits in latch 0,1,2 (solenoid 4 & 16 ON)
n+17	set bit 1 latch 2, bit 5,latch 0, reset other bits in latch 0,1,2 (solenoid 5 & 17 ON)
n+18	set bit 2 latch 2, bit 6,latch 0, reset other bits in latch 0,1,2 (solenoid 6 & 18 ON)
n+19	set bit 3 latch 2, bit 7,latch 0, reset other bits in latch 0,1,2 (solenoid 7 & 19 ON)
n+20	set bit 4 latch 2, bit 0,latch 1, reset other bits in latch 0,1,2 (solenoid 8 & 20 ON)
n+21	set bit 5 latch 2, bit 1,latch 1, reset other bits in latch 0,1,2 (solenoid 9 & 21 ON)
n+22	set bit 6 latch 2, bit 2,latch 1, reset other bits in latch 0,1,2 (solenoid 10 & 22 ON)
n+23	set bit 7 latch 2, bit 3,latch 1, reset other bits in latch 0,1,2 (solenoid 11 & 23 ON)
' second string:
n+24	set nothing (open string), reset bits in latches 3,4,5
n+25	set bit 0 latch 3, reset other bits in latch 3,4,5  (solenoid 1 ON)
n+26	set bit 1 latch 3, reset other bits in latch 3,4,5  (solenoid 2 ON)
n+27	set bit 2 latch 3, reset other bits in latch 3,4,5  (solenoid 3 ON)
n+28	set bit 3 latch 3, reset other bits in latch 3,4,5  (solenoid 4 ON)
n+29	set bit 4 latch 3, reset other bits in latch 3,4,5  (solenoid 5 ON)
n+30	set bit 5 latch 3, reset other bits in latch 3,4,5  (solenoid 6 ON)
n+31	set bit 6 latch 3, reset other bits in latch 3,4,5  (solenoid 7 ON)
n+32	set bit 7 latch 3, reset other bits in latch 3,4,5  (solenoid 8 ON)
n+33	set bit 0 latch 4, reset other bits in latch 3,4,5  (solenoid 9 ON)
n+34	set bit 1 latch 4, reset other bits in latch 3,4,5  (solenoid 10 ON)
n+35	set bit 2 latch 4, reset other bits in latch 3,4,5  (solenoid 11 ON)
n+36	set bit 3 latch 4, reset other bits in latch 3,4,5  (solenoid 12 ON)
n+37	set bit 4 latch 4, bit 0,latch 3, reset other bits in latch 3,4,5 (solenoid 1 & 13 ON) 
n+38	set bit 5 latch 4, bit 1,latch 3, reset other bits in latch 3,4,5  (solenoid 2 & 14 ON)
n+39	set bit 6 latch 4, bit 2,latch 3, reset other bits in latch 3,4,5  (solenoid 3 & 15 ON)
n+40	set bit 7 latch 4, bit 3,latch 3, reset other bits in latch 3,4,5 (solenoid 4 & 16 ON) 
n+41	set bit 0 latch 5, bit 4,latch 3, reset other bits in latch 3,4,5  (solenoid 5 & 17 ON)
n+42	set bit 1 latch 5, bit 5,latch 3, reset other bits in latch 3,4,5  (solenoid 6 & 18 ON)
n+43	set bit 2 latch 5, bit 6,latch 3, reset other bits in latch 3,4,5 (solenoid 7 & 19 ON) 
n+44	set bit 3 latch 5, bit 7,latch 3, reset other bits in latch 3,4,5  (solenoid 8 & 20 ON)
n+45	set bit 4 latch 5, bit 0,latch 4, reset other bits in latch 3,4,5  (solenoid 9 & 21 ON)
n+46	set bit 5 latch 5, bit 1,latch 4, reset other bits in latch 3,4,5 (solenoid 10 & 22 ON) 
n+47	set bit 6 latch 5, bit 2,latch 4, reset other bits in latch 3,4,5  (solenoid 11 & 23 ON)
n+48	set bit 7 latch 5, bit 3,latch 4, reset other bits in latch 3,4,5  (solenoid 12 & 24 ON)

On reception of a note OFF command, nothing should happen in PIC1's code.
On reception of all notes OFF, however, all bits should be cleared.

For first test version, take n = 40.

data-port: RB0-RB7  Port B van de PIC, alle bits geflipt: RB7 ==> D0	   pic pin 28
							  RB6 ==> D1	   pic pin 27
							  RB5 ==> D2	   pic pin 26
						          RB4 ==> D3	   pic pin 25
							  RB3 ==> D4	   pic pin 24
							  RB2 ==> D5 	   pic pin 23
							  RB1 ==> D6	   pic pin 22
							  RB0 ==> D7	   pic pin 21

===========================================================================
==== P I C 2  =============================================================
===========================================================================

PIC2 is used for bow motor control (3 output bits, 1 PWM for analog voltage)
     - 0-10V speed control for Siemens Micromaster 410
       on reception of volume controller data: 176+9, 7, data
       PIC pin 13
       The mapping should be such that we have 0-50% PWM for midi-in values 0-100, whereas the 50% 	to 100% range should be mapped on 101-127.
	CHANGE IN VERSION 1.2: PWM has to be inverted in the PIC code !!!

     - start/stop bow motor
       on reception of 176+9, 66, data  (data = 0 or >0)
       on reception of note-on commands, unless 176+9, 66, 0 was received before.
       on reception of all notes off, the bit should be reset.	
       PIC pin 2 - RA0	
	CHANGE IN VERSION 1.2: Bit has to be inverted in PIC code.

     - CW/CWW direction of bow rotation
       on reception of 176+9, 67, data  (data = 0 or >0)
       PIC pin 3 - RA1
       A change of direction should be preceded by a motor stop command.

     - new for version 1.2:
       on reception of 176+9, 68, data (data = 0 or >0)
       PIC pin 4 - RA2  should be set reset.
       Also here, the bit has to be inverted on the PIC code level.

       Following can be removed in version 1.2:
     - Ack.  send on reception of reset: clears error condition 
       on reception of 176+9, 123, 0  (all notes off)
       PIC pin 4 - RA2 

     for extra features (lights):
     - PIC pin 28 - RB7
       set/reset bit on reception of Note ON/OFF for note 0 (left frontlight)
     - PIC pin 27 - RB6 
       set/reset bit on reception of note ON/OFF for note 1 (right frontlight)
     - PIC pin 26 - RB5
       set/reset bit on reception of 176+9, 92, 0/1

=====================================================================
PIC3 is used for the bow pusher softshift solenoids (2 PWM outputs)

     - PIC pin 12 (RC1) - PWM output 0-100%
       The PWM value should correspond to the velocity byte in the note on command for the note
range n to n+23
	Note OFF command for this note range should reset the output to 0.
     - PIC pin 13 (RC2) - PWM output 0-100%
	The PWM value should correspond to the velocity byte in the note on command for the note range n+24 to n+48
	Note OFF command for this note range should reset the output to 0.

	Keypressure command should be implemented as well, so that we can change bow pressure during a note (midi command sequence 160 + k, note, value). For notes n to n+23, value should be output to PWM1, for notes n+24 to n+48, to PWM2.

All-notes-off should reset both PWM outputs.

For extra features:
	- PIC port RB (8 bit port)
	  To be implemented.     
data-port: RB0-RB7  Port B van de PIC, alle bits geflipt: RB7 ==> D0	   pic pin 28
							  RB6 ==> D1	   pic pin 27
							  RB5 ==> D2	   pic pin 26
						          RB4 ==> D3	   pic pin 25
							  RB3 ==> D4	   pic pin 24
							  RB2 ==> D5 	   pic pin 23
							  RB1 ==> D6	   pic pin 22
							  RB0 ==> D7	   pic pin 21

======================================================================
Software implementation:
Channel = 9 (&H09)
Note range: (note-on & note-off implemented):

40 to 88 (48 notes, 4 octaves)
notes out of the range should be rejected in the PIC software.

The software should have a six byte array to store the contents of the latches: la(0) to la(5)